Often high functionality digital processing devices include multiple processing engines operating in response to clock signals of different frequencies. In other words, the speed of the clocks mediating the operation of various circuit blocks and other on-chip operational units may differ, depending on the function being implemented. These various clocks typically should be synchronous, especially when correlated data, such as audio and video, are being processed.
Traditional PLL techniques allow for the generation of multiple clock frequencies with relatively simple relationships. However, these frequencies are often insufficient to support disparate processing operations. For example, while processing an audio—video data stream, the video is typically processed at a clock frequency substantially higher than that used to process the audio. Moreover, the audio and video clocks may or may not be rationally related. In other words, it may not be possible to easily generate accurate synchronous audio and video clocks by simply dividing-down or multiplying-up a master clock in a PLL or similar circuit.
Additionally, the issue of clock jitter must be addressed. On the one hand, the loop filter cut-off in a conventional PLL should be sufficiently low to reduce reference feedthrough. However, on the other hand, reducing the cut-off frequency of the loop filter increases the VCO noise that falls outside the control of the loop. In other words, some trade-off must normally be made between clock jitter caused by reference clock feedthrough and that caused by VCO noise.
In sum, new techniques are required for generating low-jitter clocks, including clocks of widely varying frequencies and/or frequency varying by non-rational factors.